This PostDoc position is within the Photonic Integration group of the Electrical Engineering Department and is part of a research line focusing on electronic photonic integration.
Photonic integrated circuits (PIC) have become increasingly more complex in recent years, driven by the demands of high-capacity information transport systems, which necessitate high-performance, parallel transceiver integration on a small footprint with low power consumption. In addition, new application areas such as RF beam steering, LIDAR and photonic signal processing emerge which continue to push the limits of PIC complexity and integration density. Embedding of PICs with driver and control electronics becomes a challenge as conventional methods limit connection density and yield undesired parasitics, posing a bottleneck for density, performance and energy efficiency. New technology approaches employing scalable 2D and 3D electronic photonic integration are needed and will be explored in the proposed work.
Prior activities in the two research projects Photronics and WIPE have established co-design methods for electronics and photonics as a potential route to high-density low parasitic 'photronic' systems. Furthermore, novel circuit design schemes that exploit this intimate connection between electronics and photonics have been explored. The candidate shall leverage the work done within these projects, to explore:
- The relative advantages and disadvantages of electronic photonic integration schemes including
- Wafer scale bonding
- Flip chip assembly
- Hybrid co-designed building blocks
- Devising methods for studying and testing 100GHz class electro-optic devices
- Identifying process level dependencies for circuit level performance
- Identifying in-line methods for predicting high speed performance