Do you want to make a difference in the emerging world of computing ushered by the open standard RISC-V?
The Computer Architecture for Embedded Systems (CAES) Chair at the University of Twente invites applications for a 4-year PhD position on the topic of "Design and Characterization of Reliable Computing Methodologies for RISC-V."
We are looking for a talented and focused researcher with a strong background in digital design and computer architecture who has the ambition to contribute to creating novel approaches to achieve high reliability in safety-critical applications and in space.
The successful applicant will be supervised by Dr. Ir. Marco Ottavi. During the four years appointment, the PhD student will have the opportunity to broaden their knowledge by joining international exchange programs, participating in national and international conferences and workshops, and visiting other research institutes and universities worldwide.
You will work within the framework of the KDT-JU-funded TRISTAN (Together for RISc-V Technology and ApplicatioNs) project. TRISTAN'S overarching aim is to expand, mature, and industrialize the European RISC-V ecosystem to compete with existing commercial alternatives.
Your project will focus on the following activities:
- Introduction of techniques to increase the reliability of a processor by detecting and correcting errors in the control flow (DUE: detected unrecoverable error) and to prevent exceptions and system hangs/crashes.
- Introduction of techniques to increase the reliability of a processor by detecting and correcting errors in the data flow (SDC: Silent Data Corruption) to prevent unintended and potentially harmful execution of the programs.
- Setup and execution of irradiation campaigns (e.g., neutrons, protons, or heavy ions) to validate the introduced modifications on the design by implementing the RISC-V architecture using a flash-based FPGA
Also, in collaboration with the other TRISTAN PhD candidate, you will explore dual-purpose modifications to the core to obtain both security and reliability enhancement.