Job description
Join the NWO Perspectief FIND program and help design next-generation computer architectures for running large AI models on embedded and edge systems under strict timing, energy, and memory constraints. You’ll explore hardware-aware optimization and co-design with accelerators (FPGAs, GPUs, near-memory systems) to achieve real-time, energy-efficient AI for high-tech industry applications. Work with leading companies like ASMPT and shape the future of AI at the edge!
Information
Industrial edge deployments—in semiconductor manufacturing, printing systems, automotive radar, smart mobility cameras, and HealthTech—require on-device AI to ensure low latency, privacy, and resilience. Today’s Transformers models scale poorly and assume abundant cloud resources. The research program FIND aims to deliver architectural and algorithmic breakthroughs that enable foundation models to run predictably and efficiently on embedded processors and accelerators.
FIND is a research program funded by the Dutch government and industry that brings together 5 universities, 11 companies (startups to multinationals), and 2 knowledge institutes to develop foundation models (large AI models) for Dutch high‑tech industry, with strong emphasis on edge deployment, privacy, and timely decision‑making. Partners include ASML, NXP, Canon, ASMPT, Technolution, Signify, Shell, Stryker, TNO, and others. A total of 12 PhDs will be employed on the FIND program covering topics from foundation model pre-training and multimodal adaptation to architectures and compression for edge deployment while targeting real-world validation in domains like HealthTech, smart industry, and autonomous mobility.
This PhD position focuses on the design of novel computer architectures to enable large AI models to run on embedded and edge systems under strict timing, energy, and memory constraints. Current solutions typically rely on general-purpose CPUs or GPUs, which are optimized for flexibility rather than predictable real-time performance. These platforms struggle with the complexity and resource demands of foundation models, leading to high latency, excessive energy consumption, and large memory footprints—making them unsuitable for safety-critical or resource-constrained environments.
In addition, you will explore model compression and co-optimization with hardware accelerators. Unlike existing approaches that apply compression techniques (e.g., pruning, quantization) in isolation, this research will jointly optimize algorithms and hardware. Co-optimization ensures that architectural decisions—such as token merging, sparsity exploitation, and quantization—are aligned with hardware datapaths and memory hierarchies. This enables predictable real-time performance, energy efficiency, and scalability across heterogeneous platforms (embedded CPUs, GPUs, FPGAs, near-memory accelerators). The result is a shift from “best-effort” execution on generic hardware to deterministic, deadline-compliant AI inference tailored for industrial edge systems.
These architectures and accelerators will be prototyped and validated in collaboration with a leading high-tech semiconductor manufacturing company, demonstrating how edge devices can execute foundation models with guaranteed performance and minimal energy footprint—closing the gap between AI capability and embedded system constraints.
Research group and company
This position is embedded in the Electronic Systems (ES) group within the Electrical Engineering department at Eindhoven University of Technology (TU/e). Our group consists of six full professors, three associate professors, seven assistant professors, several postdocs, approximately 40 EngD and PhD candidates, and support staff. The ES group is world-renowned for its design automation and embedded systems research.
This PhD project is executed in close collaboration with ASMPT which is the only company in the world offering a comprehensive portfolio of integrated solutions for all major steps in electronics manufacturing – from carrier for chip interconnection to chip assembly and packaging to SMT.