- Design InP photonic building blocks in coupon format for integration with Si-based photonic platforms
- Fabricate InP coupon wafers suitable for detachment and transfer onto silicon photonic circuits
- Develop strategies for testing of coupons and demonstrate functional heterogeneous photonic circuits
InformationPhotonic integrated circuits - or optical chips - have evolved into a mature technology with a broad spectrum of use cases and a diversity of platforms and building blocks. The foundry model is now becoming established where Process Design Kits (PDKs) allow fabless designers to create their own chips with custom functionality. While most of the early progress was based on monolithic integration, the drive for high-performance, cost-effective manufacturing of photonic integrated circuits (PICs) at scale has shifted the focus to heterogeneous integration based on silicon substrates. This approach combines the strengths of different materials within a single PIC platform. In particular, enhancing silicon platforms with efficient III-V active functions (lasers, amplifiers, modulators, detectors) requires the design and fabrication of tailored InP coupons, which can be transferred using advanced micro-transfer technologies.
We are looking for a researcher to drive the development of heterogeneous PIC platforms, with a primary focus on innovating InP coupons tailored for LIFT (laser-induced forward transfer) in close cooperation with TNO, while also contributing to advancements in established MTP (micro-transfer printing) technologies. Initial work will target InP coupons with semiconductor optical amplifiers (SOAs) for transfer onto SiN (silicon nitride) platforms. This will expand into a broader set of InP building blocks integrated on other Si-based platforms. The role will involve coupon layout design, development of low-loss optical couplers, coupon fabrication, and collaborative transfer experiments to realize demonstrator heterogeneous PICs for a sensing application (to be determined). The research will follow a rigorous design flow to deliver functional, PDK-ready building blocks, in close collaboration with colleagues working on testing, compact modeling, and platform development.
The PIC fabrication work will be carried out at the NanoLab@TU/e cleanroom facility (
http://www.tue.nl/nanolab), which hosts a state-of-the-art 4” processing line for III-V semiconductors, including an ASML DUV scanner, AIXTRON MOCVD G10 epitaxy reactor, electron beam lithography, diverse plasma etching tools, wafer-level bonding equipment and others.
The position builds on the pioneering work in the foundry production of complex photonic integrated circuits in the JePPIX Pilot Line. The appointed person will work closely with a team of InP PIC technology experts at the Photonic Integration Technology Centre (PITC) and collaborate with integrated photonics researchers. The person is expected to produce PIC building blocks that are accessible to consortium partners. This new position is within the new Chips for Europe PIXEurope Pilot Line, which brings together InP PIC technology, silicon photonics, test automation and packaging within one technology agnostic design flow with Europe's leading research organisations.
Link for PIXEurope:
https://www.tue.nl/en/news-and-events/news-overview/05-12-2024-pixeurope-consortium-to-lead-the-european-pilot-line-on-advanced-photonic-integrated-circuitsLink for PITC:
https://pitc.nl