- Design and optimize epitaxial layerstacks for lasers and modulators to meet target performance
- Execute epitaxy process steps as part of full PIC fabrication flows in collaboration with process engineers
- Develop and maintain a library of agile epitaxy processes to enable generic photonic integration
InformationPhotonic integrated circuits - or optical chips - have evolved into a mature technology with a broad spectrum of use cases and a diversity of platforms and building blocks. The foundry model is now becoming established where Process Design Kits (PDKs) allow fabless designers to create their own chips with custom functionality. While most developments have previously focused on C-band, bandgap engineering allows indium phosphide photonic circuits to operate at other wavelength ranges. To fully exploit this potential, new photonic building blocks must be developed, including lasers, modulators, photodetectors, and passive components. Extending their operation to the O-band (1310 nm) and the 2-µm band will unlock opportunities in data center interconnects as well as a broad range of sensing applications in healthcare, agrifood, mobility, and others.
We are seeking an R&D engineer to develop novel epitaxial layerstacks for photonic integrated lasers and modulators in both the O-band and 2-µm band. The work will begin at single layerstacks and evolve into multi-layerstacks integration onto the same wafer via etch-and-regrowth techniques. Through applying a strong foundation in materials science and engineering, you will design semiconductor layerstacks for optimal performance of active and passive devices. Key targets will include the accurate control of bandgap, surface morphology, doping profiles and layer interfaces, mostly focusing on AlInGaAs compounds. The epitaxy developments will contribute to novel photonic building blocks for next-generation photonic integrated platforms. Close collaboration with colleagues with device engineers and process engineers is foreseen.
The PIC fabrication work will be carried out at the NanoLab@TU/e cleanroom facility (
http://www.tue.nl/nanolab), which hosts a state-of-the-art 4” processing line for III-V semiconductors, including an ASML DUV scanner, AIXTRON MOCVD G10 epitaxy reactor, electron beam lithography, diverse plasma etching tools, wafer-level bonding equipment and others.
The position builds on the pioneering work in the foundry production of complex photonic integrated circuits in the JePPIX Pilot Line. The appointed person will work closely with a team of InP PIC technology experts at the Photonic Integration Technology Centre (PITC) and collaborate with integrated photonics researchers. The person is expected to produce PIC building blocks that are accessible to consortium partners. This new position is within the new Chips for Europe PIXEurope Pilot Line, which brings together InP PIC technology, silicon photonics, test automation and packaging within one technology agnostic design flow with Europe's leading research organisations.
Link for PIXEurope:
https://www.tue.nl/en/news-and-events/news-overview/05-12-2024-pixeurope-consortium-to-lead-the-european-pilot-line-on-advanced-photonic-integrated-circuitsLink for PITC:
https://pitc.nl