In the last 40 years the systematic downscaling of CMOS Integrated Circuit (IC) technologies has enabled unprecedented improvements in transistor density, frequency of operation, energy efficiency and reliability. CMOS technologies allow today to integrate in digital microprocessors several billion of transistors in a chip that has the size of a fingernail. While technology downscaling has been extremely beneficial for digital circuits, the design of analog frontend electronics and Analog-to-Digital converters in deep sub-micron CMOS technologies is becoming increasingly challenging due to the systematic power supply reduction, the intrinsically larger device parameter variability, and the higher low-frequency noise level of these transistors. These trends directly limit the resolution of data-converters. Moreover, to achieve automotive-worth, 5-6 sigma reliability of key performance parameters, accurate calibration loops are needed to precisely tune or compensate circuit non-idealities. Calibration of static first-order errors (for example the bandwidth variation of a filter) is straightforward and widely used. Calibration of (a multitude of) second- or higher order and dynamic errors over product lifetime, is extremely challenging in terms of prediction and extraction of (non-orthogonal) frequency dependent non-linear errors.  

This project is part of the Robust AI for Safe radar signal process (RAISE) program, sponsored by the Eindhoven AI Systems Institute (EAISI) and NXP.

Your duties

As a PhD candidate in the Integrated Circuits group, you will investigate a novel methodology to design and implement self-calibration techniques for data converters with the aid of Machine Learning (ML). During your PhD you will first identify the root causes (from a circuit perspective) responsible for data converter performance reduction due to operation in non-typical conditions or to aging effects. Next you will investigate suitable ML algorithms to periodically calibrate the data converter behavior and recover its nominal performance level. Finally, you will design a novel data converter embedding a ML-based self-calibration circuit on hardware, achieving state-of-the-art performance. Architectural, ML algorithmic and transistor-level design approaches will be considered in this challenging exploration.

In summary your main tasks will be:

• Develop a new design methodology exploiting Machine Learning to periodically self-calibrate data converters and maximize their performance by adapting to operating conditions and aging of the circuits;
• Investigate methods to efficiently train the ML algorithms using a reduced set of data points;
• Demonstrate the potential  and effectiveness of the proposed approach by designing, implementing and characterizing data converters achieving state-of-the-art performance. 
• Disseminate the results of your research in international and peer-reviewed journals and conferences;  
• Get involved in educational tasks such as the supervision of Master/Bachelor students and internships;
• Write a dissertation based on the research outcome and successfully defend it.

We are looking for a candidate who meets the following requirements:

• You have a strong background in Integrated Circuit (IC) design together with an hands-on experience with IC CAD systems.
• You have solid understanding of data converters.
• You hold a MSc degree in Electrical Engineering.
• You are a talented and enthusiastic young researcher.
• Prior knowledge of machine learning algorithms, neural and/or Bayesian networks is a plus.
• You have good programming skills (preferably Python or MATLAB).
• You have good communication skills and can work in a multidisciplinary team.
• You are proficient in spoken and written English; knowledge of Dutch is not required.
   

• A meaningful job in a dynamic and ambitious university with the possibility to present your work at international conferences.
• A full-time employment for four years, with an intermediate evaluation (go/no-go) after nine months.
• To develop your teaching skills, you will spend 10% of your employment on teaching tasks.
• To support you during your PhD and to prepare you for the rest of your career, you will make a Training and Supervision plan and you will have free access to a personal development program for PhD students. 
• At TU/e we challenge you to take charge of your own learning process.
• A gross monthly salary and benefits (such as a pension scheme, pregnancy and maternity leave, partially paid parental leave) in accordance with the Collective Labor Agreement for Dutch Universities.
• Additionally, an annual holiday allowance of 8% of the yearly salary, plus a year-end allowance of 8.3% of the annual salary.
• Should you come from abroad and comply with certain conditions, you can make use of the so-called '30% facility', which permits you not to pay tax on 30% of your salary.
• A broad package of fringe benefits, including an excellent technical infrastructure, moving expenses, and savings schemes.
• Family-friendly initiatives are in place, such as an international spouse program, and excellent on-campus children day care and sports facilities.