In the last 40 years, the systematic downscaling of CMOS Integrated Circuit (IC) technologies has enabled unprecedented improvements in the transistor density, frequency of operation, energy efficiency and reliability. Most recent CMOS technologies allow the integration of several billions of transistors in a digital microprocessor chip the size of a fingernail. However, the design of ICs in advanced CMOS technology nodes requires heavy verification tests based on simulations to estimate the achieved circuit performance prior manufacturing. As circuit complexity increases, so does the required simulations time and thus the verification costs. Consequently, the development of next generation electronic solutions will require increasing time-to markets as well as significant investments of the semiconductor industry in human-labor resources leading to higher costs and potentially limited availability of consumer electronic solutions.

In this scenario, within the Integrated Circuits (IC) group we are currently investigating new verification approaches and design methodologies based on Machine Learning (ML) models which aim to shorten the simulation time by 10x. However, the data required to train these ML models needs also to be generated by means of circuit simulations. Therefore, smart and efficient training of the models which minimizes the number of datapoints is of paramount important for the success of this research.

This project is done in cooperation with NXP semiconductors, Eindhoven.

Your duties

As a postdoctoral researcher from the Integrated Circuits group, you will mainly focus on the investigation of smart sampling techniques e.g., based on Bayesian optimization to efficiently train the Machine Learning models used in the circuit simulator. During your 1-year employment you will directly conduct the research. Moreover, you will be involved in the supervision of a PhD student and a MSc student working on related topics.